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Lattice Semiconductor
Correlator IP Core
In this example, two channels and two different coef?cient sequences have been con?gured. Each channel can be
correlated to either of the two coef?cient sequences.
Figure 2. User Interface Timing Diagram for Two-channel Correlator
Figure 3. User Interface Timing Diagram for Two-channel Correlator
The user drives the irdy signal high for one clock cycle indicating that the input values are valid. Along with the
input data, the user also sets the block_start_in signal. This signal will be taken as a marker by the Correlator
and aligned with the input data as it passes through the Correlator IP core. The next time the block_start_out
signal is set and chan_out = 0, it will indicate that the output data was associated with this input data value. The
block_start signals act as markers for the user to do frame alignments between the input and outputs of the
Correlator IP core. This is necessary since the core operates on one input data sample at a time. It does not per-
form multiple correlations over “num_lag” values as expressed in Equation 1. This allows the simplest and most
versatile Correlator IP core design. If it is necessary to operate for multiple “lags,” then the user application will
need to add input and output FIFOs around the core to feed data values one sample at time.
At time 178.5μs, crdy again goes active indicating that the Correlator IP core is ready to accept the next input
value, and in the example of Figure 2 the user inputs data for channel 1. At time 196.5μs, the correlation result for
channel 0 is ready at the dout outputs, and the core outputs a value of 0x9 on dout , sets the chan_out to 0, and
asserts the ordy signal. It also asserts the block_start_out signal to indicate that this output value was asso-
ciated with the din value from time 175.5μs.
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